1 www.pericom.com pi6c491 1506-06 reva 1 1/02/2012 00 01 1x osc d le q q0 nq0 q5 nq5 6 lvpecl outputs pullup pullup pulldown pulldown pulldown pulldown clk_en clk_sel0 clk_sel1 xtal_in xtal_out clk0 clk1 nclk1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nq2 q2 v dd nq1 q1 v ee nq0 q0 clk_sel0 xtal_in xtal_out clk_en q3 nq3 v dd q4 nq4 v dd q5 nq5 clk_sel1 nclk1 clk1 clk0 features ? 6 lvpecl outputs ? up to 1.5ghz output frequency ? ultra low additive phase jitter: < 0.03 ps (typ) (diferential 156.25mhz, 12khz to 20mhz integration range) ? selectable reference inputs support either single-ended or diferential or xtal ? low skew between outputs within banks (<40ps) ? low delay from input to output (tpd typ. 1.5ns) ? separate input output supply voltage for level shifing ? 2.5v / 3.3v power supply ? industrial temperature support ? tssop-24 package pi6c4911506-06 block diagram pin confguration (24-pin tssop) low skew, 1-to-6, crystal/lvcmos/differential - 3.3v, 2.5v lvpecl fanout buffer description te pi6c4911506-06 is a high performance lvpecl fanout bufer device that accepts crystal, single ended and diferential inputs. te part supports up to 1.5ghz frequency. tis device is ideal for systems that need to distribute low jitter clock signals to multiple destinations. 12-0290
2 www.pericom.com pi6c491 1506-06 reva 1 1/02/2012 pi6c4911506-06 low skew, 1-to-6, crystal/lvcmos/diferantial - 3.3v, 2.5v lvpecl fanout bufer pin # pin name type description 1, 2 nq2, q2 output diferential output pair. lvpecl interface levels 3, 19, 22 v dd power power supply pins 4, 5 nq1, q1 output diferential output pair. lvpecl interface levels 6 v ee power negative supply pin 7, 8 nq0, q0 output diferential output pair. lvpecl interface levels 9, 16 clk_sel0, clk_sel1 input pulldown clock select pins. lvcmos/lvttl interface levels. see table 3b 10 xtal_in input parallel resonant crystal interface. xtal_in is the input 11 xtal_out output parallel resonant crystal interface. xtal_out is the output 12 clk_en input pullup synchronizing clock enable. when high, clock outputs follow clock input when low, the outputs are disabled lvcmos / lvttl interface levels. see table 3a 13 clk0 input pulldown lvcmos/lvttl clock input 14 clk1 input pulldown non-inverting diferential clock input 15 nclk1 input pullup inverting diferential clock input 17, 18 nq5, q5 output diferential output pair. lvpecl interface levels 20, 21 nq4, q4 output diferential output pair. lvpecl interface levels 23, 24 nq3, q3 output diferential output pair. lvpecl interface levels note: 1. pullup and pulldown refer to internal input resistors. see table "pin characteristics" on page 6, for typical values. pinout table 12-0290
3 www.pericom.com pi6c491 1506-06 reva 1 1/02/2012 pi6c4911506-06 low skew, 1-to-6, crystal/lvcmos/diferantial - 3.3v, 2.5v lvpecl fanout bufer lvcmos / lvttl dc characteristics, v dd = 3.3v5% or 2.5v5%, v ee = 0v, t a = -40c to 85c symbol parameter test condition min. typ. max. units v ih input high voltage v dd = 3.3v 2 v dd +0.3 v v dd = 2.5v 1.7 v dd +0.3 v il input low voltage v dd = 3.3v -0.3 0.8 v dd = 2.5v -0.3 0.7 i ih input high current clk0, clk_sel0:1 v dd = v in = 3.465v or 2.625v 150 a clk_en v dd = v in = 3.465v or 2.625v 20 i il input low current clk0, clk_sel0:1 v dd = 3.465v or 2.625v, v in = 0v -15 clk_en v dd = 3.465v or 2.625v, v in = 0v -150 maximum ratings (above which the useful life may be impaired. for user guidelines, not tested) storage temperature ...................................................- 55 to +150oc s upply voltage to ground potential (vdd) .......... - 0.5 to +4.6v inputs (referenced to gnd) ...........................- 0.5 to vdd+0.5v c lock output (referenced to gnd)...............-0.5 to vdd+0.5v s oldering temperature (max of 10 seconds) ....................+ 260oc latch up ..................................................................................2 00ma note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. maximum ratings (above which the useful life may be impaired. for user guidelines, not tested) storage temperature ...................................................- 55 to +150oc s upply voltage to ground potential (vdd) .......... - 0.5 to +4.6v inputs (referenced to gnd) ...........................- 0.5 to vdd+0.5v c lock output (referenced to gnd)...............-0.5 to vdd+0.5v s oldering temperature (max of 10 seconds) ....................+ 260oc latch up ..................................................................................2 00ma esd protection (input) .................................. 2 000 v min (hbm) note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. power supply characteristics and operating conditions symbol parameter test condition min. typ. max. units v dd core supply voltage 3.135 3.465 v 2.375 2.625 v i dd core power supply current outputs unloaded 150 ma t a ambient operating temperature -40 85 c 12-0290
4 www.pericom.com pi6c491 1506-06 reva 1 1/02/2012 pi6c4911506-06 low skew, 1-to-6, crystal/lvcmos/diferantial - 3.3v, 2.5v lvpecl fanout bufer differential dc characteristics, v dd = 3.3v5% or 2.5v5%, v ee = 0v, t a = -40c to 85c symbol parameter test condition min. typ. max. units v cmr common mode input voltage 1,2 v ee +0.5 v dd -0.85 v v pp peak-to-peak input voltage 1 0.15 1.3 i il input low current nclk1 v dd = 3.465v or 2.625v, v in = 0v -150 a clk1 v dd = 3.465v or 2.625v, v in = 0v -5 i ih input high current nclk1 v dd = v in = 3.465v or 2.625v 5 clk1 v dd = v in = 3.465v 150 note: 1. v il should not be less than -0.3v. 2. common mode voltage is defned as v cmr . crystal characteristics parameter test condition min. typ. max. units mode of oscillation fundamental frequency 12 40 mhz equivalent series resistance (esr) 50 shunt capacitance 7 pf drive level 1 mw note: 1. characterized using an 18pf parallel resonant crystal. dc electrical specifcations- lvpecl outputs parameter description conditions min. typ. max. units v oh output high voltage v dd =3.3v 2.1 2.6 v v dd =2.5v 1.3 1.6 v ol output low voltage v dd =3.3v 1.3 1.8 v v dd =2.5v 0.5 0.8 12-0290
5 www.pericom.com pi6c491 1506-06 reva 1 1/02/2012 pi6c4911506-06 low skew, 1-to-6, crystal/lvcmos/diferantial - 3.3v, 2.5v lvpecl fanout bufer ac characteristics, v dd = 3.3v5%, v ee = 0v, t a = -40c to 85c symbol parameter test condition min. typ. max. units f max output frequency clk1/nclk1 1500 mhz clk0 300 t pd propagation delay 1a, 1b 1.5 ns tjit bufer additive jitter, rms clk1/nclk1, 156.25mhz, integration range: 12khz - 20mhz 0.03 ps tsk(o) output skew 2 55 ps tsk(pp) part-to-part skew 3 450 ps t r / t p output rise/fall time 20% to 80% 120 350 ps odc output duty cycle 48 52 % ac characteristics, v dd = 2.5v5%, v ee = 0v, t a = -40c to 85c symbol parameter test condition min. typ. max. units f max output frequency clk1/nclk1 1500 mhz clk0 300 t pd propagation delay 1a, 1b 1.5 ns tjit bufer additive jitter, rms clk1/nclk1, 156.25mhz, integration range: 12khz - 20mhz 0.03 ps tsk(o) output skew 2 55 ps tsk(pp) part-to-part skew 3 450 ps t r / t p output rise/fall time 20% to 80% 120 350 ps odc output duty cycle 48 52 % note: 1a. measured from the diferential input crossing point to the diferential output crossing point. 1b. measured from v dd /2 input crossing point to the diferential output crossing point. 2. defned as skew between outputs at the same supply voltage and with equal load conditions. 3. defned as skew between outputs on diferent devices operating at the same supply voltages and with equal load conditions. 12-0290
6 www.pericom.com pi6c491 1506-06 reva 1 1/02/2012 pi6c4911506-06 low skew, 1-to-6, crystal/lvcmos/diferantial - 3.3v, 2.5v lvpecl fanout bufer pin characteristics symbol parameter conditions min typ max units c in input capacitance 4 pf r pulldown input pulldown resistor clk0, clk1 51 k r pullup input pulup resistor nclk1 51 k inputs outputs clk_en clk_sel1 clk_sel0 selected source q0:q5 nq0:nq5 0 0 0 xtal low high 0 0 1 clk0 low high 0 1 x clk1/ nclk1 low high 1 0 0 xtal enabled enabled 1 0 1 clk0 enabled enabled 1 1 x clk1/ nclk1 enabled enabled control input function table confguration test load board termination for lvpecl v 100 150 z = 50 l = 0 ~ 10in 150 device o z = 50 o dd tla tla 12-0290
7 www.pericom.com pi6c491 1506-06 reva 1 1/02/2012 pi6c4911506-06 low skew, 1-to-6, crystal/lvcmos/diferantial - 3.3v, 2.5v lvpecl fanout bufer packaging mechanical: 24-contact tssop (l) ordering code package code package type operating temperature PI6C4911506-06LIE l pb-free & green, 24-pin tssop -40c to 85c note: 1. termal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. e denotes pb-free and green 3. adding an x at the end of the ordering code denotes tape and reel packaging date: 05/03/12 description: 24-pin, 173mil wide tssop package code: l document control #: pd-1312 revision: f notes: 1. refer jedec: mo-153f/ad 2. controlling dimensions in millimeters 3. package outline exclusive of mold flash and metal burr 12-0374 12-0290
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